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<meta name="description" content="Verilog 最常用的 2 种数据类型就是线网（wire）与寄存器（reg），其余类型可以理解为这两种数据类型的扩展或辅助。   线网（wire）  wire 类型表示硬件单元之间的物理连线，由其连接的器件输出端连续驱动。如果没有驱动元件连接到 wire 型变量，缺省值一般为 “Z”。举例如下：    实例 [mycode4 type=&#039;verilog&#039;] wire   interrupt ; wire   fla..">
		
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				<h2>2.3 Verilog 数据类型</h2>				<h3><em>分类</em> <a href="../w3cnote_genre/verilog" title="Verilog 教程" >Verilog 教程</a> </h3>
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					<p>Verilog 最常用的 2 种数据类型就是线网（wire）与寄存器（reg），其余类型可以理解为这两种数据类型的扩展或辅助。</p>


<h3>线网（wire）</h3>

<p>wire 类型表示硬件单元之间的物理连线，由其连接的器件输出端连续驱动。如果没有驱动元件连接到 wire 型变量，缺省值一般为 "Z"。举例如下：
</p>


<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">wire</span> &nbsp; interrupt <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">wire</span> &nbsp; flag1<span style="color: #5D478B;">,</span> flag2 <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">wire</span> &nbsp; gnd <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span> &nbsp;<br />
</div></div>


<p>线网型还有其他数据类型，包括 wand，wor，wri，triand，trior，trireg 等。这些数据类型用的频率不是很高，这里不做介绍。</p>

<h3>寄存器（reg）</h3>

<p>寄存器（reg）用来表示存储单元，它会保持数据原有的值，直到被改写。声明举例如下：</p>


<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp;clk_temp<span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">reg</span>    flag1<span style="color: #5D478B;">,</span> flag2 <span style="color: #5D478B;">;</span><br />
</div></div>


<p>例如在 always 块中，寄存器可能被综合成边沿触发器，在组合逻辑中可能被综合成 wire 型变量。寄存器不需要驱动源，也不一定需要时钟信号。在仿真时，寄存器的值可在任意时刻通过赋值操作进行改写。例如： </p>


<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">reg</span> rstn <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; rstn <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">100</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; rstn <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">end</span><br />
</div></div>


<h3>向量</h3>
<p>
当位宽大于 1 时，wire 或 reg 即可声明为向量的形式。例如：</p>


<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp;counter <span style="color: #5D478B;">;</span>    <span style="color: #00008B; font-style: italic;">//声明4bit位宽的寄存器counter</span><br />
<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">32</span><span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp;gpio_data<span style="color: #5D478B;">;</span>   <span style="color: #00008B; font-style: italic;">//声明32bit位宽的线型变量gpio_data</span><br />
<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">8</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#93;</span>     addr <span style="color: #5D478B;">;</span>       <span style="color: #00008B; font-style: italic;">//声明7bit位宽的线型变量addr，位宽范围为8:2</span><br />
<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">31</span><span style="color: #9F79EE;">&#93;</span>     data <span style="color: #5D478B;">;</span>       <span style="color: #00008B; font-style: italic;">//声明32bit位宽的寄存器变量data, 最高有效位为0</span><br />
</div></div>


<p>对于上面的向量，我们可以指定某一位或若干相邻位，作为其他逻辑使用。例如：</p>


<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">9</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; data_low <span style="color: #5D478B;">=</span> data<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">9</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span><br />
addr_temp<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">=</span> addr<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">8</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">7</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">+</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
</div></div>


<p>Verilog 支持可变的向量域选择，例如：</p>


<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">31</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; data1 <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp;byte1 <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">integer</span> j <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">always</span><span style="color: #5D478B;">@*</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">for</span> <span style="color: #9F79EE;">&#40;</span>j<span style="color: #5D478B;">=</span><span style="color: #ff0055;">0</span><span style="color: #5D478B;">;</span> j<span style="color: #5D478B;">&lt;=</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">;</span>j<span style="color: #5D478B;">=</span>j<span style="color: #5D478B;">+</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; byte1<span style="color: #9F79EE;">&#91;</span>j<span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">=</span> data1<span style="color: #9F79EE;">&#91;</span><span style="color: #9F79EE;">&#40;</span>j<span style="color: #5D478B;">+</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">*</span><span style="color: #ff0055;">8</span><span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span> <span style="color: #5D478B;">:</span> j<span style="color: #5D478B;">*</span><span style="color: #ff0055;">8</span><span style="color: #9F79EE;">&#93;</span><span style="color: #5D478B;">;</span> <br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//把data1[7:0]…data1[31:24]依次赋值给byte1[0][7:0]…byte[3][7:0]</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<span style="color: #A52A2A; font-weight: bold;">end</span><br />
</div></div>

<p>
<strong>Verillog 还支持指定 bit 位后固定位宽的向量域选择访问。</strong></p>
<ul><li>
<strong>[bit+: width]</strong> :  从起始 bit 位开始递增，位宽为 width。
</li><li>
<strong>[bit-: width]</strong> :  从起始 bit 位开始递减，位宽为 width。
</li></ul>

<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #00008B; font-style: italic;">//下面 2 种赋值是等效的</span><br />
A <span style="color: #5D478B;">=</span> data1<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">31</span><span style="color: #5D478B;">-:</span> <span style="color: #ff0055;">8</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span><br />
A <span style="color: #5D478B;">=</span> data1<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">31</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">24</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span><br />
<br />
<span style="color: #00008B; font-style: italic;">//下面 2 种赋值是等效的</span><br />
B <span style="color: #5D478B;">=</span> data1<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #5D478B;">+</span> <span style="color: #5D478B;">:</span> <span style="color: #ff0055;">8</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span><br />
B <span style="color: #5D478B;">=</span> data1<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">7</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span><br />
</div></div>


<p><strong>对信号重新进行组合成新的向量时，需要借助大括号。例如：</strong></p>


<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">31</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;temp1<span style="color: #5D478B;">,</span> temp2 <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">assign</span> temp1 <span style="color: #5D478B;">=</span> <span style="color: #9F79EE;">&#123;</span>byte1<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #5D478B;">,</span> data1<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">31</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">8</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#125;</span><span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//数据拼接</span><br />
<span style="color: #A52A2A; font-weight: bold;">assign</span> temp2 <span style="color: #5D478B;">=</span> <span style="color: #9F79EE;">&#123;</span><span style="color: #ff0055;">32</span><span style="color: #9F79EE;">&#123;</span><span style="color: #ff0055;">1'b0</span><span style="color: #9F79EE;">&#125;</span><span style="color: #9F79EE;">&#125;</span><span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//赋值32位的数值0 &nbsp;</span><br />
</div></div>



<h3>整数，实数，时间寄存器变量</h3>
<p>
整数，实数，时间等数据类型实际也属于寄存器类型。</p>
<p>
<strong>整数（integer）</strong></p>

<p>整数类型用关键字 integer 来声明。声明时不用指明位宽，位宽和编译器有关，一般为32 bit。reg 型变量为无符号数，而 integer 型变量为有符号数。例如：</p>


<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">31</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp;data1 <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; byte1 <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//数组变量，后续介绍</span><br />
<span style="color: #A52A2A; font-weight: bold;">integer</span> j <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//整型变量，用来辅助生成数字电路</span><br />
<span style="color: #A52A2A; font-weight: bold;">always</span><span style="color: #5D478B;">@*</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">for</span> <span style="color: #9F79EE;">&#40;</span>j<span style="color: #5D478B;">=</span><span style="color: #ff0055;">0</span><span style="color: #5D478B;">;</span> j<span style="color: #5D478B;">&lt;=</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">;</span>j<span style="color: #5D478B;">=</span>j<span style="color: #5D478B;">+</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; byte1<span style="color: #9F79EE;">&#91;</span>j<span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">=</span> data1<span style="color: #9F79EE;">&#91;</span><span style="color: #9F79EE;">&#40;</span>j<span style="color: #5D478B;">+</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">*</span><span style="color: #ff0055;">8</span><span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span> <span style="color: #5D478B;">:</span> j<span style="color: #5D478B;">*</span><span style="color: #ff0055;">8</span><span style="color: #9F79EE;">&#93;</span><span style="color: #5D478B;">;</span> <br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//把data1[7:0]…data1[31:24]依次赋值给byte1[0][7:0]…byte[3][7:0]</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<span style="color: #A52A2A; font-weight: bold;">end</span><br />
</div></div>


<p>此例中，integer 信号 j 作为辅助信号，将 data1 的数据依次赋值给数组 byte1。综合后实际电路里并没有 j 这个信号，j 只是辅助生成相应的硬件电路。
</p>
<p><strong>实数（real）</strong></p>

<p>实数用关键字 real 来声明，可用十进制或科学计数法来表示。实数声明不能带有范围，默认值为 0。如果将一个实数赋值给一个整数，则只有实数的整数部分会赋值给整数。例如：</p>


<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">real</span> &nbsp; &nbsp; &nbsp; &nbsp;data1 <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">integer</span> &nbsp; &nbsp; temp <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; data1 <span style="color: #5D478B;">=</span> 2e3 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; data1 <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">3.75</span> <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp;<br />
<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; temp <span style="color: #5D478B;">=</span> data1 <span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//temp 值的大小为3</span><br />
<span style="color: #A52A2A; font-weight: bold;">end</span><br />
</div></div>


<p><strong>时间（time）</strong></p><p>
Verilog 使用特殊的时间寄存器 time 型变量，对仿真时间进行保存。其宽度一般为 64 bit，通过调用系统函数 $time 获取当前仿真时间。例如：</p>


<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">time</span>       current_time <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
       <span style="color: #5D478B;">#</span><span style="color: #ff0055;">100</span> <span style="color: #5D478B;">;</span><br />
       current_time <span style="color: #5D478B;">=</span> <span style="color: #9932CC;">$time</span> <span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//current_time 的大小为 100</span><br />
<span style="color: #A52A2A; font-weight: bold;">end</span><br />
</div></div>


<h3>数组</h3>

<p>在 Verilog 中允许声明 reg, wire, integer, time, real 及其向量类型的数组。</p>

<p>数组维数没有限制。线网数组也可以用于连接实例模块的端口。数组中的每个元素都可以作为一个标量或者向量，以同样的方式来使用，形如：<span class="marked">&lt;数组名&gt;[&lt;下标&gt;]</span>。对于多维数组来讲，用户需要说明其每一维的索引。例如：</p>

<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">integer</span>          flag <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//8个整数组成的数组</span><br />
<span style="color: #A52A2A; font-weight: bold;">reg</span>  <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span>       counter <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//由4个4bit计数器组成的数组</span><br />
<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span>       addr_bus <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//由4个8bit wire型变量组成的数组</span><br />
<span style="color: #A52A2A; font-weight: bold;">wire</span>             data_bit<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">5</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//声明1bit wire型变量的二维数组</span><br />
<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">31</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span>       data_4d<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">11</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">255</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//声明4维的32bit数据变量数组</span><br />
</div></div>


<p>下面显示了对数组元素的赋值操作：</p>

<div class="example"><h2 class="example">实例</h2> <div class="example_code">
flag <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#93;</span> &nbsp; <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">3</span><span style="color: #ff0055;">2'd0</span> <span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//将flag数组中第二个元素赋值为32bit的0值</span><br />
counter<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">4'hF</span> <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//将数组counter中第4个元素的值赋值为4bit 十六进制数F，等效于counter[3][3:0] = 4'hF，即可省略宽度; </span><br />
<span style="color: #A52A2A; font-weight: bold;">assign</span> addr_bus<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">=</span> <span style="color: #ff0055;">8'b0</span> <span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//将数组addr_bus中第一个元素的值赋值为0</span><br />
<span style="color: #A52A2A; font-weight: bold;">assign</span> data_bit<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b1</span><span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//将数组data_bit的第1行第2列的元素赋值为1，这里不能省略第二个访问标号，即 assign data_bit[0] = 1'b1; 是非法的。</span><br />
data_4d<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">15</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1</span><span style="color: #ff0055;">5'd3</span> <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//将数组data_4d中标号为[0][0][0][0]的寄存器单元的15~0bit赋值为3</span><br />
</div></div>


<p>虽然数组与向量的访问方式在一定程度上类似，但不要将向量和数组混淆。向量是一个单独的元件，位宽为 n；数组由多个元件组成，其中每个元件的位宽为 n 或 1。它们在结构的定义上就有所区别。
</p>

<h3>存储器</h3><p>

存储器变量就是一种寄存器数组，可用来描述 RAM 或 ROM 的行为。例如：
</p>

<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; membit<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">255</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//256bit的1bit存储器</span><br />
<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp;mem<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">1023</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span> &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//1Kbyte存储器，位宽8bit</span><br />
mem<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">511</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">8'b0</span> <span style="color: #5D478B;">;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//令第512个8bit的存储单元值为0</span><br />
</div></div>


<h3>参数</h3><p>

参数用来表示常量，用关键字 parameter 声明，只能赋值一次。例如：</p>

<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">parameter</span>     &nbsp;data_width <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1</span><span style="color: #ff0055;">0'd32</span> <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">parameter</span>      i<span style="color: #5D478B;">=</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">,</span> j<span style="color: #5D478B;">=</span><span style="color: #ff0055;">2</span><span style="color: #5D478B;">,</span> k<span style="color: #5D478B;">=</span><span style="color: #ff0055;">3</span> <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">parameter</span>      mem_size <span style="color: #5D478B;">=</span> data_width <span style="color: #5D478B;">*</span> <span style="color: #ff0055;">10</span> <span style="color: #5D478B;">;</span><br />
</div></div>


<p>但是，通过实例化的方式，可以更改参数在模块中的值。此部分以后会介绍。</p>
<p>局部参数用 localparam 来声明，其作用和用法与 parameter 相同，区别在于它的值不能被改变。所以当参数只在本模块中调用时，可用 localparam 来说明。</p>


<h3>字符串</h3>

<p>字符串保存在 reg 类型的变量中，每个字符占用一个字节（8bit）。因此寄存器变量的宽度应该足够大，以保证不会溢出。</p>

<p>字符串不能多行书写，即字符串中不能包含回车符。如果寄存器变量的宽度大于字符串的大小，则使用 0 来填充左边的空余位；如果寄存器变量的宽度小于字符串大小，则会截去字符串左边多余的数据。例如，为存储字符串 "run.runoob.com", 需要 14*8bit 的存储单元：</p>


<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #5D478B;">:</span> <span style="color: #ff0055;">14</span><span style="color: #5D478B;">*</span><span style="color: #ff0055;">8</span><span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; str <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; str <span style="color: #5D478B;">=</span> <span style="color: #FF00FF;">&quot;run.runoob.com&quot;</span><span style="color: #5D478B;">;</span> <br />
<span style="color: #A52A2A; font-weight: bold;">end</span> &nbsp;<br />
</div></div>

<p>
有一些特殊字符在显示字符串中有特殊意义，例如换行符，制表符等。如果需要在字符串中显示这些特殊的字符，则需要在前面加前缀转义字符 <span class="marked">\</span> 。例如下表所示：</p>

<table class="reference"><thead><tr><th style="text-align:left;"><span>转义字符</span></th><th style="text-align:left;"><span>显示字符</span></th></tr></thead><tbody><tr><td style="text-align:left;"><span>\n</span></td><td style="text-align:left;"><span>换行</span></td></tr><tr><td style="text-align:left;"><span>\t</span></td><td style="text-align:left;"><span>制表符</span></td></tr><tr><td style="text-align:left;"><span>%%</span></td><td style="text-align:left;"><span>%</span></td></tr><tr><td style="text-align:left;"><span>\</span></td><td style="text-align:left;"><span>\</span></td></tr><tr><td style="text-align:left;"><span>\"</span></td><td style="text-align:left;"><span>"</span></td></tr><tr><td style="text-align:left;"><span>\ooo</span></td><td style="text-align:left;"><span>1到3个8进制数字字符</span></td></tr></tbody></table>
<p>其实，在 SystemVerilog（主要用于 Verilog 仿真的编程语言）语言中，已经可以直接用关键字 string 来表示字符串变量类型，这为 Verilog 的仿真带来了极大的便利。有兴趣的学者可以简单学习下 SystemVerilog。</p>				</div>
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	<li><a target="_top" data-id="22851" title="1.2 Verilog 简介" href="../w3cnote/verilog-intro.html" >1.2 Verilog 简介</a></li>
	
		
	<li><a target="_top" data-id="22852" title="1.3 Verilog 环境搭建" href="../w3cnote/verilog-install.html" >1.3 Verilog 环境搭建</a></li>
	
		
	<li><a target="_top" data-id="22866" title="1.4 Verilog 设计方法" href="../w3cnote/verilog-design-method.html" >1.4 Verilog 设计方法</a></li>
	
		
	<li><a target="_top" data-id="22869" title="2.1 Verilog 基础语法" href="../w3cnote/verilog-basic-syntax.html" >2.1 Verilog 基础语法</a></li>
	
		
	<li><a target="_top" data-id="22870" title="2.2 Verilog 数值表示" href="../w3cnote/verilog-number.html" >2.2 Verilog 数值表示</a></li>
	
		<li>
	2.3 Verilog 数据类型	</li>
	
		
	<li><a target="_top" data-id="22872" title="2.4 Verilog 表达式" href="../w3cnote/verilog-expression.html" >2.4 Verilog 表达式</a></li>
	
		
	<li><a target="_top" data-id="22935" title="2.5 Verilog 编译指令" href="../w3cnote/verilog-compile-instruction.html" >2.5 Verilog 编译指令</a></li>
	
		
	<li><a target="_top" data-id="22931" title="3.1 Verilog 连续赋值" href="../w3cnote/verilog-assign.html" >3.1 Verilog 连续赋值</a></li>
	
		
	<li><a target="_top" data-id="22933" title="3.2 Verilog 时延" href="../w3cnote/verilog-time-delay.html" >3.2 Verilog 时延</a></li>
	
		
	<li><a target="_top" data-id="22936" title="4.1 Verilog 过程结构" href="../w3cnote/verilog-process-structure.html" >4.1 Verilog 过程结构</a></li>
	
		
	<li><a target="_top" data-id="22939" title="4.2 Verilog 过程赋值" href="../w3cnote/verilog-process-assign.html" >4.2 Verilog 过程赋值</a></li>
	
		
	<li><a target="_top" data-id="22941" title="4.3 Verilog 时序控制" href="../w3cnote/verilog-timing-control.html" >4.3 Verilog 时序控制</a></li>
	
		
	<li><a target="_top" data-id="22943" title="4.4 Verilog 语句块" href="../w3cnote/verilog-statements-block.html" >4.4 Verilog 语句块</a></li>
	
		
	<li><a target="_top" data-id="22948" title="4.5 Verilog 条件语句" href="../w3cnote/verilog-condition-statement.html" >4.5 Verilog 条件语句</a></li>
	
		
	<li><a target="_top" data-id="22950" title="4.6 Verilog 多路分支语句" href="../w3cnote/verilog-case.html" >4.6 Verilog 多路分支语句</a></li>
	
		
	<li><a target="_top" data-id="22951" title="4.7 Verilog 循环语句" href="../w3cnote/verilog-loop.html" >4.7 Verilog 循环语句</a></li>
	
		
	<li><a target="_top" data-id="22954" title="4.8 Verilog 过程连续赋值" href="../w3cnote/verilog-deassign.html" >4.8 Verilog 过程连续赋值</a></li>
	
		
	<li><a target="_top" data-id="22966" title="5.1 Verilog 模块与端口" href="../w3cnote/verilog-module-port.html" >5.1 Verilog 模块与端口</a></li>
	
		
	<li><a target="_top" data-id="22969" title="5.2 Verilog 模块例化" href="../w3cnote/verilog-generate.html" >5.2 Verilog 模块例化</a></li>
	
		
	<li><a target="_top" data-id="22972" title="5.3 Verilog 带参数例化" href="../w3cnote/verilog-defparam.html" >5.3 Verilog 带参数例化</a></li>
	
		
	<li><a target="_top" data-id="22975" title="6.1 Verilog 函数" href="../w3cnote/verilog-function.html" >6.1 Verilog 函数</a></li>
	
		
	<li><a target="_top" data-id="22982" title="6.2 Verilog 任务" href="../w3cnote/verilog-task.html" >6.2 Verilog 任务</a></li>
	
		
	<li><a target="_top" data-id="22990" title="6.3 Verilog 状态机" href="../w3cnote/verilog-fsm.html" >6.3 Verilog 状态机</a></li>
	
		
	<li><a target="_top" data-id="22999" title="6.4 Verilog 竞争与冒险" href="../w3cnote/verilog-competition-hazard.html" >6.4 Verilog 竞争与冒险</a></li>
	
		
	<li><a target="_top" data-id="23008" title="6.5 Verilog 避免 Latch" href="../w3cnote/verilog-latch.html" >6.5 Verilog 避免 Latch</a></li>
	
		
	<li><a target="_top" data-id="23011" title="6.6 Verilog 仿真激励" href="../w3cnote/verilog-testbench.html" >6.6 Verilog 仿真激励</a></li>
	
		
	<li><a target="_top" data-id="23015" title="6.7 Verilog 流水线" href="../w3cnote/verilog-pipeline-design.html" >6.7 Verilog 流水线</a></li>
	
		
	<li><a target="_top" data-id="23021" title="7.1 Verilog 除法器设计" href="../w3cnote/verilog-dividend.html" >7.1 Verilog 除法器设计</a></li>
	
		
	<li><a target="_top" data-id="23222" title="7.2 Verilog 并行 FIR 滤波器设计" href="../w3cnote/verilog-fir.html" >7.2 Verilog 并行 FIR 滤波器设计</a></li>
	
		
	<li><a target="_top" data-id="23230" title="7.3 Verilog 串行 FIR 滤波器设计" href="../w3cnote/verilog-serial-fir.html" >7.3 Verilog 串行 FIR 滤波器设计</a></li>
	
		
	<li><a target="_top" data-id="23236" title="7.4 Verilog CIC 滤波器设计" href="../w3cnote/verilog-cic.html" >7.4 Verilog CIC 滤波器设计</a></li>
	
		
	<li><a target="_top" data-id="23260" title="7.5 Verilog FFT 设计" href="../w3cnote/verilog-fft.html" >7.5 Verilog FFT 设计</a></li>
	
		
	<li><a target="_top" data-id="23309" title="7.6 Verilog DDS 设计" href="../w3cnote/verilog-dds.html" >7.6 Verilog DDS 设计</a></li>
	
		
	<li><a target="_top" data-id="23281" title="8.1 Verilog 数值转换" href="../w3cnote/verilog-numerical-conversion.html" >8.1 Verilog 数值转换</a></li>
	
	<li><a target="_top" title="Verilog 教程高级篇" href="../w3cnote/verilog2-tutorial.html" >Verilog 教程高级篇</a></li></ul></div>	</div>
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